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products and specifications discussed herein are subject to change by micron without notice. 09005aef80c07280 MT9V403_ds.fm - rev. b 1/04 en 1 ?2004 micron technology, inc. 1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 1/2-inch cmos active- pixel cmos image sensor MT9V403 micron part number: MT9V403c12st features ? array format: active: 659h x 494v pixel size and type: 9.9m x 9.9m truesnap? (shuttered-node active pixel) optical format: 1/2-inch frame rate: 0-200 fram es/sec progressive scan data rate: 66 mb/s (master clock 66 mhz) responsivity: 2.0 v/lux-sec with source illumination at 550nm snr: 45db adc: on-chip, 10-bit power: 130mw at 200 fps supply voltage: +3.3v internal intra-scene dynamic range: 60db operating temperature: -5c to +70c output: 10-bit digital through a single port shutter: truesnap freeze-frame electronic shutter interface mode: master/snapshot/slave (with simultaneous or sequential exposure/readout) shutter efficiency: 98.5% shutter exposure time: master mode or snapshot mode: 2 rows to 256 frames (20s to 1.3 sec with 66 mhz clock) slave mode: user controlled gain: 1x?18x (step size = 1) or 0.5x?9x (step size = 0.5) control interface: two- wire serial interface package: 48-pin clcc timing and control: on-chip: adc controls, output multiplexing, adc calibra- tion via two-wire serial interface, exposure time, read/write adc calibration coefficients, window size and location, gain, biases, master vs. snap- shot vs. slave, simultaneous vs. continuous expo- sure/readout, progressive vs. interlace, adc reference, vertical and horizontal blanking. off-chip: exposure trigger (snapshot mode), exposure and readout timing (slave mode) color specifications: monochrome or color (bayer pattern) description the micron ? imaging MT9V403 vga-based cmos active-pixel sensor has a 1/2-inch optical format and delivers superb resolution at a turbocharged 200 fps, making it the perfect solution for machine vision assembly lines, airbag depl oyment, golf swing analysis, and special effects in movies. the freeze-frame shutter allows the signal charges of all pixels to be integrated in parallel?all pixels star t integrating simultaneously and stop integrating simult aneously. the charges are then sampled into pixel analog memories (one mem- ory per pixel) and consequently, row by row, are digi- tized and read out-of-chip. the sensor works in master, snapshot, or slave mode. in master mode it generates the readout timing on-chip. in snapshot mode it accepts an external trigger and then generates the readout timing. in slave mode the sensor accepts external readout timing. th e integration time is pro- grammed through the two-wire serial interface (mas- ter or snapshot mode) or controlled via externally- generated control signals (slave mode). the scanning mode can be progressive or inter- laced. there is also an option to scan just a window of interest by choosing star t row and column and stop row and column. the user can control the frame rate and row rate through the use of vertical and horizontal blanking as well as the master clock frequency. the readout of the data out of the chip can be done simultaneously with integration and adc operation due to the two-cell sram which allows data from the previously converted row to be shifted into the output memory for readout. the sensor?s adcs contain special self-calibrating circuitry that allow the sensor to reduce its own col- umn-wise fixed pattern noise. the calibration coeffi- cients can be read from, and written to, the sensor.
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 2 ?2004 micron technology. inc. figure 1: block diagram reset expose frame row sensor interface block control logic row decoder pixel array column pga column adcs and calibration memory 667h x 10 sram (x2) adc and output registers gain control calibration data readout control two-wire serial interface output (9:0) system clock system clock system data table 1: pin description pin numbers signal name type descriptions 37 sysclk input clock input for entire chip. maximum desi gn frequency is 66 mhz (50 percent, 5 percent duty cycle). 33 lrst_n input global logic reset function (asynchron ous). active low pu lse with minimum duration 200ns. 30 row_strt input slave mode input signal. starts row proce ssing sequence of th e pixel row (i.e., pixel readout, adc conversion, and writin g of data to adc registers). the rising edge of row_strt should be synchronous with the fa lling edge of sysclk. a one-clock cycle wide active high pulse. the two-wire serial interface register setting switches this pin between input and output. 31 ld_shft_n input slave mode input sign al. an active low signal that enables the column counter and initiates the readout process. causes the 10-bit output port to be updated with data on the rising edge of the sy stem clock. the two-wire serial interface register setting switches this pin between input and output. 29 expose input trigger for snapshot mode . the two-wire serial interface register setting switches this pin between input and output. no connection should be made in slave mode. 26 pg_n input slave mode input signal. active low pu lse that resets all photodetectors, starting a new integration cycle. no connection should be made in master mode or snapshot mode. 25 tx_n input slave mode input signal. active low puls e that controls trans fer of charge from photodetector to memory in side each pixel for the entire pixel array. no connection should be made in master mode or snapshot mode. 24 resmem input slave mode input signal. active low pu lse to reset all pixel memories. no connection should be made in master mode or snapshot mode. 38 sclk input serial port clock. maximum frequency is 1 mhz. 18 vlns input bias setting voltage for vln_amp or vln_out. vln_amp and vln_out can be individually disconnected from their in ternal biases via the two-wire serial interface and driven by this input. 17 vln1 input bias setting voltage for pixel so urce following operating current. 19 vlp input bias setting voltage for the column source follower operating current. 13 voff input dark offset cancellation. polarity of offset is set via the two-wire serial interface. 16 v ref input op amp bias.
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 3 ?2004 micron technology. inc. 9v ref 1 input adc reference voltage that sets the ma ximum input signal level, setting the size of the least significant bit (lsb) in the analog to digita l conversion process. 8v ref 1drv input adc bias. 7v ref 2 input adc reference used for the calibration operation. 32 frame_sync_n input slave mode input signal. active low pu lse to reset row an d column counters, providing frame synchronization. low du ration should be at least two-clock cycles wide. an input that is held low also sets the sensor in low, per standby mode, until it is released. signal is pulled up on-chip. 14 vtest input the user should ground this pin. 23 vrstlow input offset that may be needed for very short exposure conditions. 21 vln2 input bias setting voltage for the adc operating current. 39 sdata input/ output serial port data. 30 frame_valid output master mode and snapshot mode output signal. active high during readout. the two-wire serial interface register se tting switches this pin between input and output. 31 row_valid output master mode and snapshot mode output signal. active high when image data are on data output bus. the two-wire se rial interface register setting switches this pin between input and output. 29 expose output master mode output signal. active high during exposure. the two-wire serial interface register setting switches this pin between input and output. 41 data9 output pixel output data bit 9 (msb). 40 data8 output pixel output data bit 8. 45 data7 output pixel output data bit 7. 42 data6 output pixel output data bit 6. 46 data5 output pixel output data bit 5. 47 data4 output pixel output data bit 4. 48 data3 output pixel output data bit 3. 1data2output pixel output data bit 2. 2data1output pixel output data bit 1. 3data0output pixel output data bit 0 (lsb). 12, 22 v aa power 3.3v power supply fo r analog signal pr ocessing circuitry. 20 vrst_pix power power supply for pixel array. set for 2.5v. 10, 11, 15 a gnd power ground for analog signal processing circuitry. 6, 27, 36, 43 v dd power 3.3v digital power supply. 4, 5, 28, 34, 35, 44 d gnd power ground for digital circuitry. table 1: pin description (continued) pin numbers signal name type descriptions
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 4 ?2004 micron technology. inc. pixel data format the pixel array descriptions and details are shown below. figure 2: pixel array description figure 3: pixel color pattern detail (bottom left corner) output format and timing the sensor can operate in three interface modes: master, snapshot, or slave mode. additionally, master mode can be setup to allow simultaneous integration and readout (simultaneous master mode) or sequen- tial integration and readout (sequential master mode). mode selection is done via the two-wire serial inter- face, taking less than one frame time to switch between modes. the default register settings program the imager to read out the visible pixels. therefore, the start row is 1, start column is 9, end row is 480 and the end column is 648. master mode in master mode the sensor internally generates the timing to initiate exposure and readout. the interface signals utilized in master mode are depicted in figure 4. in master mode, the start of the integration period is determined internal to the MT9V403. figure 4: master mode interface signals the integration time is pre-programmed via the two-wire serial interface and indicated by the expose signal going high. when the sensor commences, the readout process the frame_valid, row_valid, and data signals are output, as shown in figure 5 on page 5. the master mode row synchronization waveform relationships are as shown in figure 5 on page 5. the frame_valid signal goes high, indicating the start of frame, and 2.5 clock cycles later the row_valid signal goes high, indicating the start of the first row. the first data bit is valid on the first falling edge of sysclk after row_valid goes high. the remaining 665 pixels for the row are valid on the subsequent fall- ing edges of sysclk, after which row_valid returns to the low state. (please note that in master mode 648 pixels are readout for each row.) the row_valid will then be an active high envelope for subsequent rows and the frame_valid signal will be an active high envelope for subsequent frames. the time required for one complete row operation is 671 clock cycles: 1 clock cycle delay + 666 columns + 4 clock cycles when row_valid is low. with a sysclk of 66 mhz, this translates into a row time of 10.2s and a frame time of 5.1ms for full resolution (502 rows). this assumes there is no vertical blanking or horizontal blanking and that the exposure time is less than 5.1ms. if exposure time becomes greater than 5.1ms, the frame time then becomes the inverse of the exposure time (1/[exposure time]). active pixel array 8 8 659 494 dark and isolation pixels (1, 1) (502, 667) black pixels g b g b g b g r g r g r g r g b g b g b g r g r g r g r g b g b g b g r g r g r g r g b g b g b g expose mt9v4o3 sysclk frame_valid row_valid data lrst_n controller
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 5 ?2004 micron technology. inc. figure 5: master mode row timing diagram note: horizontal blanking is nominally 35 rows, and may be increased using register 5. in master mode the frame rate is controlled by inserting vertical and/or horizontal blanking periods during readout, or by changing the input master clock (sysclk) frequency (i.e., slowing the sensor down), or by changing the number of rows being readout (i.e., window size). table 2 shows some examples of how the frame rate changes with window resolution and clock speed. table 2: frame rate vs. resolution and clock speed no blanking, exposure < readout when horizontal blanking is utilized, the row_valid stays low for an additional user-pro- grammable number of clock cycles after each row readout. as a result the row time becomes: rt = (1 + 66 6+ 4 + hb) x (1/fsysclk) where hb is the horizontal blanking in sysclk cycles (255 clock maximum) specified in register 5. when vertical blanking is utilized, the frame_ valid signal stays low for an additional user pro- grammable number of rows after the frame is readout (if exposure time < readout time) or exposed (if expo- sure time > readout time). table 3 on page 6 shows the various scenarios for calculating the frame time, where vb is the vertical blanking in rows (255 rows maxi- mum) specified in register 6. the default vertical blanking is one sysclk cycle, so the true vertical blanking time is the numb er of blanking rows pro- grammed plus one clock cycle. horizontal blanking sysclk (input) row _valid (output) data [9:0] (output) 1 xxx xxx 12 653 671 671 + 169 1 12 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 9 10 648 649 910 ( ) ( ) 652 resolution (# rows) clock speed (sysclk) frame rate (frames/second) 502 (full resolution) 66 mhz 196 251 66 mhz 392 125 66 mhz 784 63 66 mhz 1568 502 (full resolution) 24 mhz 70 251 24mhz 140 125 24 mhz 280 63 24 mhz 560 502 (full resolution) 10 mhz 30
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 6 ?2004 micron technology. inc. table 3: determination of frame timing note: n = number of rows in image rt = row time vb = vertical blanking rows (255 rows maximum); set in register 6 hb = horizontal blanking in sysclk cycles (255 maximum); set forth in register 6 simultaneous master mode there are two possible operation methods for mas- ter mode: simultaneous master mode and sequential master mode. one of these operation modes must be selected via the two-wire se rial interface. in simulta- neous master mode the exposure period occurs during readout. the frame synchronization waveforms are shown in figure 6 and figure 7. this is the fastest mode of operation since the exposure and readout are happening in parallel rather than sequentially. please note that with this speed optimized timing the first row readout is the last row of the previous frame that is still in the row memory. figure 6: simultaneous master mode frame synchronization waveforms readout time > exposure time note: vertical blanking is nominally 1 sysclk and 0 row times, and may be increased by using register 6. figure 7: simultaneous master mode frame synchronization waveforms exposure time > readout time note: vertical blanking is nominally 1 sysclk and 0 row times, and may be increased by using register 6. exposure time > readout time readout time > exposure time no blanking frame time = exposure time frame time = n x rt with vertical blanking frame time = exposure time + vb frame time = (n + vb) x rt vertical blanking expose (output) frame_valid (output) row_valid (output) data [9:0] (output) exposure time xxx xxx row 2 row 1 row n row n-1 row 479 row 478 row 481 row 1 row 2 xxx xxx xxx row 480 row n row n-1 row 479 row 478 xxx row 480 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) vertical blanking expose (output) frame_valid (output) row_valid (output) data [9:0] (output) exposure time xxx xxx row 2 row 1 row 479 row 478 row 1 row 2 row 480 row 479 row 478 row 480 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) row 481
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 7 ?2004 micron technology. inc. sequential master mode in sequential master mode the exposure period is followed by readout. the frame synchronization wave- forms for sequential master mode are shown in figure 8. figure 8: sequential master mo de frame synchronization waveforms note: vertical blanking is nominally 1 sysclk and 0 row times, and may be increased by using register 6. snapshot mode in snapshot mode the sensor accepts an input trig- ger signal that initiates exposure, which is immediately followed by readout. the interface signals utilized in snapshot mode are depicted in figure 9. in snapshot mode the start of the integration period is determined by the externally applied expose pulse that the user inputs to the MT9V403. the integration time is prepro- grammed via the two-wire interface. after each frame's integration period is complete, the readout process commences and the frame_valid, row_ valid, and data signals are output. snapshot mode can be used to capture a single image or a sequence of images. the frame rate is con- trolled only by changing the period of the user sup- plied expose pulse train. the frame synchronization waveforms for snapshot mode are shown in figure 9. insertion of horizontal blan king periods (specified via the two-wire serial interface register) during readout is allowed, but the user controls the vertical blanking by controlling the input expose pulse. figure 9: snapshot mode interface signals figure 10: snapshot mode frame synchronization waveforms vertical blanking expose (output) frame_valid (output) row_valid (output) data [9:0] (output) xxx xxx row 2 row 1 row 479 row 478 row 1 row 2 row 480 row 479 row 478 row 480 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) xxx expose mt9v4o3 sysclk frame_valid row_valid data lrst_n controller expose (input) frame_valid (output) row_valid (output) data [9:0] (output) xxx xxx row 2 row 1 row 479 row 478 row 1 row 2 row 480 row 479 row 478 row 480 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) exposure time row_valid goes high after (2.5 + (column start -1)) clocks + 1 row time * * xxx
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 8 ?2004 micron technology. inc. slave mode slave mode allows the user much greater control of the sensor. the interface signals utilized in slave mode are depicted in figure 11. the user can start and stop integration through the use of pg_n and tx_n, respectively. the use of the resmem signal to reset pixel memories prior to ending exposure (tx_n) is optional. the readout process is controlled by user- supplied row control signals (row_strt and ld_shft_n). additionally, the frame_sync _n sig- nal may be used for frame synchronization. figure 11: slave mode interface signals figure 12 on page 9 shows the block diagram of the sensor for slave mode operation, where the sensor's digital block requires external synchronization inputs to trigger generation of the row conversion and read- out sequence. the internal structure of the digital block in slave mode includes row counter, column counter, and row sequencer. the rising edge of the row_strt signal increments the row counter to the next value and triggers the row sequencer. the row sequence duration is always equal to 671 clocks, which is fixed by the column parallel architecture. the dura- tion of the row_strt signal should be one clock cycle. the column counter selects the column output sram cells for off-chip readout at the speed of sysclk. ld_shft_n enable s the column counter when low. data is output 3.5 clocks after ld_shft_n goes low. the column counter is zeroed when ld_shft_n is high; if ld_shft is not high the counter will continue. the row counter and column counter may be zeroed using the clear signal, which is driven by reg- ister 14. the user can set th e clear signal by writing to this register through the two-wire serial interface or by pulling down the frame_sync_n signal for two clock cycles. when operating in slave mode, the user should keep in mind that both the row and column counters count between the start and stop values, which are set in registers 1?4 via the two-wire serial interface. suffi- cient time should be allocated to allow the counters to complete. it must also be emphasized that the row sequencer always requires 671 clock cycles indepen- dent of the start and stop values (i.e., window size). horizontal blanking may be achieved between rows by holding ld_shft_n high and delaying the applica- tion of the row_strt rising edge. additionally, it is possible to operate the sensor in a pipelined manner or non-pipelined manner in slave mode (master mode is alwa ys pipelined). pipelined operation means that a row of data is read out of the sensor at the same time that a new row is converted. this is accomplished through the dual sram banks that store one row for readout in one bank while the other bank is being filled with a newly converted row. as mentioned above, the row_strt triggers the row conversion and ld_shft_n enables the data output. these can be applied nearly simultaneously to achieve pipelined operation or applied sequentially, offset by the row processing time, for non-pipelined operation. note: to reduce horizontal temporal noise in slave mode, delay readout by 80 sysclk. mt9v4o3 frame_sync_n row_strt pg_n tx_n sysclk ld_shft_n data lrst_n controller
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 9 ?2004 micron technology. inc. figure 12: slave mode block diagram simultaneous slave mode there are two possible operation methods for slave mode: simultaneous slave and sequential slave mode. the method of operation selected is determined by the means in which the user supplies the control signals. in simultaneous slave mode the exposure period occurs during readout. the row and frame synchroni- zation waveforms are shown in figures 13 and 14, respectively. this is the fastest mode of operation since the exposure and readout are happening in parallel rather than sequentially. the pg_n, tx_n, and res- mem pulses should have a minimum duration of 338 clock cycles and be applied between the 100th and 600th clocks of a given row. row counter (1 to 502 max) row sequencer (1 to 671) column counter (1 to 667 max) two-wire serial interface tx_n resmem pg_n frame_sync_n row_strt clear clear clear reg14 ld_shft_n sysclk output(9:0) 667 x a10 output sram (x2) row driver pixel array column processing circuitry (pga, adc)
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 10 ?2004 micron technology. inc. figure 13: simultaneous slave mode row timing diagram example (default settings) figure 14: simultaneous slave mode frame synchronization waveforms example sysclk (input) pg_n/tx_n/ resmem (input) frame_sync_n (input) row_strt (input) ld_shft_n (input) data [9:0] (output) 1 >100 minimum 338 sysclk <600 671 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) xxx xxx xxx ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 9 10 647 648 9 10 pg_n (input) resmem (input) tx_n (input) frame_sync_n (input) row_strt (input) ld_shft_n (input) data [9:0] (output) exposure time ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) row 502 row 1 row n-1 row 2 row n row 499 row 500 row 501 row 502 row 1 row n-1 row 2 row n row 499 row 500 row 501
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 11 ?2004 micron technology. inc. sequential slave mode in sequential slave mode the exposure period is fol- lowed by readout. the row and frame synchronization waveforms are shown in figures 15 and 16, respec- tively. figure 15: sequential slave mo de row timing diagram example figure 16: sequential slave mode fr ame synchronization waveforms example sysclk (input) resmem (input) tx_n (input) frame_sync_n (input) row_strt (input) ld_shft_n (input) data [9:0] (output) 1 minimum 338 sysclk >10 sysclk 671 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) xxx xxx ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) >10 sysclk 1 2 3 666 4 667 1 2 pg_n (input) resmem (input) tx_n (input) frame_sync_n (input) row_strt (input) ld_shft_n (input) data [9:0] (output) exposure time ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) exposure time minimum duration 338 sysclk minimum duration 338 sysclk ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) row 4 row 502 row 497 row 1 row 2 row 3 row 501 row 500 row 499 row 498 row 4 row 502 row 497 row 1 row 2 row 3 row 501 row 500 row 499 row 498
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 12 ?2004 micron technology. inc. to increase intrascene dynamic range of the sensor in slave mode, the user can implement dual sampling. this is possible by applyi ng an additional tx pulse during the integration period. by doing this, one com- bines two photo signals after different exposures. figure 17 shows an example of the timing. n1 is the number of rows in the first exposure. n2 is the number of rows in the second exposure. n1 = 502 for the full frame exposure time. the intrascene dynamic range capability of the sensor is extended by the factor n1/ n2. for n1 = 500 and n2 = 2, the dynamic range enhancement is approximately 48 db. figure 18 shows output signal vs. photocurrent. the knee point is dependent on the vrstlow bias, which determines the charge capacity of the photodiode. the saturation level of photodiode must be less than the saturation level of the adc. setting vrstlow to 1.2v is enough for the default gain settings. the slope of the curve after the knee point or compression level is deter- mined by the n1/n2 ratio. figure 17: extended high dyna mic range timing in slave mode figure 18: output si gnal vs. photocurrent tx_n pg_n data [9:0] exposure n1 n2 xxx xxx ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) readout time iph signal adc saturation level ri compressed region
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 13 ?2004 micron technology. inc. serial bus description registers are written to and read from the MT9V403 through the two-wire serial interface bus. the MT9V403 is a two-wire se rial interface slave with device id "1011100x" and is controlled by the two-wire serial interface clock (sclk), which is driven by the two-wire serial interface master. data is transferred into and out through the two-wire serial interface data (sdata) line. the sdata line is pulled up to 3.3v off- chip by a 1.5k ? resistor. either the slave or master device can pull the sdata line down?the two-wire serial interface protocol determines which device is allowed to pull the sdata line down at any given time. protocol the two-wire serial host interface bus defines sev- eral different transmissi on codes, as follows: a start bit the slave device eight-bit address a(n) (no) acknowledge bit an eight-bit message a stop bit sequence a typical read or write sequence begins by the mas- ter sending a start bit. after the start bit, the master sends the slave device's eight-bit address. the last bit of the address determines if the request will be a read or a write, where a ?0? indicates a write (i.e., address b8h) and a ?1? indicates a read (i.e., address b9h). the slave device acknowledges its address by sending an acknowledge bit back to the master. if the request was a write, the master then transfers the eight-bit register address to which a write should take place. the slave sends an acknowledge bit to indi- cate that the register address has been received. the master then transfers the data eight bits at a time, with the slave sending an acknowledge bit after each eight- bits. the MT9V403 uses a 16-bit data for its internal registers, thus requiring two eight-bit transfers to write to one register. to write/read this 16-bit data, first per- form a write/read the eight msbs, then perform another write/read for eight lsbs. after 16 bits are transferred, the register address should be incre- mented, so that the next 16 bits are written to the next register address. the master stops writing by sending a start or stop bit. a typical read sequence is executed as follows. first the master sends the write-mode slave address and eight-bit register address, just as in the write request. the master then sends a start bit and the read-mode slave address. the master then clocks out the register data eight bits at a time. the master sends an acknowl- edge bit after each eight-bit transfer. the register address should be incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. bus idle state the bus is idle when both the data and clock lines are high. control of the bus is initiated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits. start bit the start bit is defined as a high-to-low transition of the data line while the clock line is high. stop bit the stop bit is defined as a low-to-high transition of the data line while the clock line is high. slave address the eight-bit address of a two-wire serial interface device consists of seven bits of address and one bit of direction. a ?0? in the lsb of the address indicates write mode, and a ?1? indicates read mode. data bit transfer one data bit is transferred during each clock pulse. the two-wire serial interface clock pulse is provided by the master. the data must be stable during the high period of the two-wire serial interface clock?it can only change when the two-wire serial interface clock is low. data is transferred eight bits at a time, followed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pulse. the transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence.
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 14 ?2004 micron technology. inc. two-wire serial interface samp le write and read sequences example of a 16-bit write sequence a typical write sequence for writing 16 bits to a reg- ister is shown in figure 19. a start bit given by the mas- ter, followed by the write address, starts the sequence. the image sensor will then give an acknowledge bit and expects the register address to come first, followed by the 16-bit data. after each eight bit, the image sen- sor will give an acknowledge bit. all 16 bits must be written before the register will be updated. after 16 bits are transferred, the register address should be incre- mented, so that the next 16 bits are written to the next register. the master stops writing by sending a start or stop bit. figure 19: timing diagram showing a write to register 9 with the value 644 example of a 16-bit read sequence a typical read sequence is shown in figure 20. first the master has to write the register address, as in a write sequence. then a start bit and the read address specifies that a read is ab out to happen from the regis- ter. the master then clocks out the register data eight bits at a time. the master sends an acknowledge bit after each eight-bit transfer. the register address should be incremented after every 16 bits is trans- ferred. the data transfer is stopped when the master sends a no-acknowledge bit. figure 20: timing diagram showing a read from register 9; returned value is 642 sclk sdata start ack b8h addr ack ack ack stop 0000 0010 1000 0100 reg0x09 sclk sdata start ack b8b addr b9h addr 0000 0010 reg0x09 ack ack ack stop 1000 0010 nack
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 15 ?2004 micron technology. inc. registers table 4: complete register description read/ write control register name function default contents register address read only reg0 chip version. 0000001100000001 00000000 w/r reg1 row start address. *******000000001 00000001 w/r reg2 column start address. ******0000001001 00000010 w/r reg3 stop row address. *******111100000 00000011 w/r reg4 stop column address. ******1010001000 00000100 w/r reg5 number of blank columns (horizontal blanking). ********10101001 00000101 w/r reg6 number of blank rows (vertical blanking). ********00100011 00000110 w/r reg7 control mode. bit 0 = 1 simultaneous mode. bit 0 = 0 sequ ential mode. bit 1 = 1 snapshot mode. bit 2 = 1 master mode. bits 3?7 not used; set to 0. possible combin ations are?00000101,? ?00000100,? ?00000010,? ?00000000?. the last combination means slave mode. ********00000101 00000111 w/r reg8 number of frame times in integration time. ********00000000 00001000 w/r reg9 number of rows times in integration time. maximum = 502. minimum = 2. *******111110110 00001001 w/r reg10 interlaced mode control. bit 0 = 1 interlaced mode 1. readout of both fields even and odd. bit 1 = 1 interlac ed mode 1 = 2. readout of only one field ? even or odd. depends on start row. bits 2?7 not used; set to 0 ********00000000 00001010 w/r reg12 calibration control. bit 0 = 1 calibration at the beginning of every frame. ********00000000 00001100 w/r reg13 dark offset enable and pixel memory reset pulse duration control. bit 0 = 1 long reset pulse. bit 1 = 1 dark offset of adc input signal using voff is enabled. bits 2?7 not used; set to 0. ********00000000 00001101 w/r reg14 clear signal control. bit 0 = 1 reset row an d column counters in digital block. sensor is in idle mode. the two-wire serial interface works and it is still possible to write/read in registers. changes of registers conten t follows without delay. normally, change of register content occurs only at the beginning of next frame in cases where the two-wire serial interface data is not busy. ********00000000 00001110 write only reg15 adc calibration data input register. *********0000000 00001111 w/r reg16 vln_amp bias control. bit 7 = 1 disable internal bias. bit 0 = 1 high bias. bit 1 = 1 low bias. bits 3?6, 8?15 not used, set to 0. 0000000000000000 00010000
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 16 ?2004 micron technology. inc. w/r reg17 vln2 bias control. bit 7 = 1 disable internal bias. bit 0 = 1 high bias. bit 1 = 1 low bias. bits 3?15 not used, set to 0. 0000000000000000 00010001 w/r reg18 vln_out bias control. bit 7 = 1disable internal bias. bit 0 = 1 high bias. bit 1 = 1 low bias. bits 3?6, 8?15 not used, set to 0. 0000000000000000 00010010 w/r reg19 vln1 bias control. bit 7 = disable internal bias. bit 0 = 1 high bias. bit 1 = 1 low bias. bits 3?6, 8?15 not used, set to 0. 0000000000000000 00010011 w/r reg20 vlp bias control. bit 7 = 1 disable internal control. bit 0 = 1 high bias. bit 1 = 1 low bias. bits 3?6, 8?15 not used, set to 0. 0000000000000000 00010100 w/r reg21 v ref bias control. bit 0-3 = bias value. bit 7 = 1 disable internal bias. bits 4?6, 8?15 not used, set to 0. 0000000000001010 00010101 w/r reg22 v ref 2 bias control. bit 0-3 bias value. bit 7= 1 disable internal bias. bits 4?6, 8?15 not used, set to 0. 0000000000001010 00010110 w/r reg23 voff bias control. bit 0-3 bias value. bit 6 = 1 sign of offset is negative. bit 7 = 1 disable internal bias. bits 4?5, 8?15 not used, set to 0. 0000000000000000 00010111 w/r reg29 vln2 bias booster. bit 3 = 1 high bias. 0000000000000000 00011101 w/r reg43 blue gain settings. default gain is 2. gain settings range is from 1 (00000001) to 18 (00010010). ********00000010 00101011 w/r reg44 green 1 gain settings. default gain is 2. gain settings range is from 1 (00000001) to 18 (00010010). ********00000010 00101100 w/r reg45 green 2 gain settings. default gain is 2. gain settings range is from 1 (00000001) to 18 (00010010). ********00000010 00101101 w/r reg46 red gain settings. default gain is 2. gain settings range is from 1 (00000001) to 18 (00010010). ********00000010 00101110 w/r reg53 global gain control. bit 0 = 1 gain is multiplied by factor of 0.5 *********0000000 00110101 table 4: complete regist er description (continued) read/ write control register name function default contents register address
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 17 ?2004 micron technology. inc. register start-up sequence upon powering up the MT9V403, the sensor should be reset by bringing the lrst_n pin low. this will ini- tialize all of the registers to their default values. upon the release of reset, the sensor will perform adc cali- bration. the default mode is simultaneous master mode with the horizontal blanking register set to 169 and the vertical blanking register set to 35. the default frame size is 648 x 480 pixels, excluding dark pixels. the first frame starts just three sysclk cycles after the end of calibration and the integration process takes place during this frame but va lid data for the first pixel row is not output until the second frame. all two-wire serial interface parameters can be writ- ten to registers at any time but they do not take effect until the subsequent frame. writing to two-wire serial interface registers has no effect on the output timing (i.e., it does not slow down or stop output); the excep- tion to this rule is when the sensor is commanded to perform adc calibration. feature description signal path an example of the signal path is shown below in figure 21. figure 21: signal path w/r reg59 v ref 1 bias control. bits 0-3 bias value. bit 7 = 1 disable internal bias. bits 4-6, 8-15 not used, set to 0. 0000000000001100 0011101 read only reg143 adc calibration data output register. *********0000000 10001111 table 4: complete regist er description (continued) read/ write control register name function default contents register address vlp pixel photo detector pixel memory column processing sample & hold adc calibration to adc registers offset voff/20 v ref 2 7 10 v ref 1 vln2 adc dac vrst_pix v aa reset memory switch (resmem) start exposure switch (pg) end exposure switch (tx) buffer buffer pga - + vln1 vln_amp v ref v ln _ out
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 18 ?2004 micron technology. inc. window location and size there is also an option to scan just a window of interest by using the two-wire serial interface to spec- ify the coordinates of the upper right most pixel and the lower left most pixel to define the desired window- ing area as shown in figure 22. the user can increase the frame rate by decreasing the number of rows in a window. decreasing the number of columns has no effect on frame rate. for example, for the full 667 col- umn by 502 row resolution the MT9V403 operates at 196 fps, but if the vertical resolution is decreased by half (i.e., 251 rows) the frame rate increases propor- tionally so the frame rate is doubled to 392 fps. figure 22: windowing example when windowing is utilized, the user should be aware of how the sensor timing is impacted. a key point to note is that the row time is always 671 clock cycles, independent of how many columns are actually read out of the sensor. figure 23 provides a master mode row timing example for windowing from column 100 to column 200. this shows how changing the num- ber of columns in a window will not change the timing nor the frame rate. figure 24 provides a master mode frame timing example for windowing from row 300 to row 400. this shows how changing the number of rows in a window will increase the frame rate. figure 23: row timing for master mo de and snapshot mode with windowing figure 24: frame timing for master mode and snapshot mode with windowing (1, 1) (502,667) start window (row,column) stop window (row,column) sysclk (input) row_valid (output) data [9:0] (output) 1 671 1 ( ) ( ) xxx xxx xxx xxx ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) start column stop column 101 100 200 199 101 100 200 199 vertical blanking frame_valid (output) row_valid (output) data [9:0] (output) xxx xxx row 301 row 300 row n row n-1 row 398 row 397 row 300 row 301 xxx xxx row 399 row n row n-1 row 398 row 397 row 399 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) start row stop row
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 19 ?2004 micron technology. inc. in slave mode the user has more control of the sen- sor but the same basic rules apply; the row time is still always 671 clock cycles. figure 25 provides a slave mode row timing example for windowing from column 100 to column 200. the row processing is initiated by raising row_strt and requires 671 clock cycles to complete. the user can readout the desired window of columns by lowering ld_shft_n and the specified columns will appear on the output with a 3.5 sysclk delay. even though the windowed columns can be readout at the beginning of a row, the user must still wait the required 671 clock cycles for the row process- ing to complete before initiating the processing of the next row with row_strt. figure 26 provides a slave mode frame timing example for windowing from row 300 to row 400 which?similar to the master mode? shows how changing the number of rows in a window will increase the frame rate. figure 25: row timing fo r slave mode with windowing figure 26: frame timing fo r slave mode with windowing sysclk (input) row_strt (input) ld_shft_n (input) data [9:0] (output) 1 1 3.5 sysclk delay start column 671 stop column ( ) ( ) ( ) ( ) xxx ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 101 100 200 199 102 frame_sync_n (input) row_strt (input) ld_shft_n (input) data [9:0] (output) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) start row stop row row 301 row 395 row 396 row 397 row 399 row 398 row 400 row 300 row 301 row 302 row 303 row 395 row 400 row 300 row 302 row 303 row 396 row 397 row 398 row 399
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 20 ?2004 micron technology. inc. electronic shutter exposure control for the master and snapshot mode the electronic shutter's exposure duration (integration time) is pro- grammed via the two-wire serial interface. the MT9V403 shutter can be operated to generate continu- ous video output (simultaneous master mode or sequential master mode) or capture single images (snapshot mode). the minimum integration time in master or snap- shot mode is 2 row times. with a 66 mhz sysclk the minimum integration time is 20s (10s row time 2 rows). the maximum integratio n time is either is 256 frame times (1.3 sec @ 200 fps) or the inverse of the frame rate. when in simultaneous master mode, the maximum integration time is limited by the inverse of the frame rate because one cannot integrate longer than a frame time. with a 66 mhz clock and full resolution (502 rows) the maximum integration time is 5ms (= 1/200 fps). in sequential master mode or snapshot mode the maximum integratio n time is limited to 256 frame times. table 5 shows some examples of how the maximum integration time changes with resolution and clock speed. table 5: maximum integration time vs. resolution and clock speed sequential mode or snapshot mode readout scanning the MT9V403 can operate in either progressive scan or interlaced scan modes. progressive scan is the default mode. in the interlace scan mode there are two readout options. the frame synchronization wave- forms for interlaced scanning are shown in figure 27, which shows alternating readout of the even-num- bered and odd-numbered rows in consecutive frames. there is also an option that allows sequential readout of only the odd or even rows of a frame (effectively a x2 vertical subsampling of the image). figure 27: frame synchronization waveforms for inte rlaced scanning resolution (# of rows) clock speed (sysclk) frame time {= n x 671 x 1/fsysclk} maximum integration time 502 (full resolution) 66 mhz 5.1ms 1.3 sec 251 66 mhz 2.6ms 0.7 sec 125 66 mhz 1.3ms 0.3 sec 63 66 mhz 0.6ms 0.2 sec 502 (full resolution) 24 mhz 14ms 3.6 sec 251 24 mhz 7ms 1.8 sec 125 24 mhz 5.1ms 0.9 sec 63 24 mhz 1.8ms 0.4 sec 502 (full resolution) 10 mhz 33ms 8 sec row 2 row 4 row 494 row 493 row 1 frame_valid row_valid odd field marker
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 21 ?2004 micron technology. inc. gain settings there are four independent gain controls which are programmed via the two-wire serial interface. the four gains correspond to four cells of the bayer pattern color filter array: red, green1, blue, and green2. the gain step size can be set to 1 or 0.5. when the step size is 1 the gain can programmed in 18 steps from x1 to x18. when the step size is 0.5, the gain can be pro- grammed 18 steps from x1 to x9. global gain control is achieved by changing the four gains equally and simultaneously. to obtain the desired analog signal chain gain, set the following registers as shown in table 6. analog biases vln1, vlp, voff, v ref , v ref 1, vln2 v ref 2, vln_amp, and vln_out are generated on-chip and can be adjusted via a two-wi re serial interface. also, the user may disable internal bias via a two-wire serial interface and apply external voltages to the sensor. v ref 1drv is generated on-chip but its internal bias cannot be disabled. vrst_pix and vrstlow are not generated internally and external voltages must be applied. considerations when setting analog voltages the starting point for setting the analog voltages should be the values suggested in the typical values columns of the tables 7 and 8. additionally, figure 21 on page 17, the ?signal path diagram,? indicates how the analog voltages affect the image. other consider- ations follow: vrstlow: functions as a pixel anti-blooming con- trol. for high illumination conditions (typically used in conjunction with a short in tegration time) black/white spots may appear. to eliminate these artifacts, this voltage should be set to ~ 0.4v. once set, this value should not have to be ch anged for different imaging conditions. vln2: internal default value should be used as the starting point. vln2 controls the current in the adc comparators and there is a safe range where this volt- age has no effect; settings below this range will cause the comparators to fail. for high-speed operation, vln2 may need to be increased to remove random white spots. vln2 may be further increased with regis- ter 17 by setting bit 0 to ?1.? if this does not completely solve the problem, set bit 7 in register 18 to disable vln_out. vrst_pix: should be set to 2.5v. v ref 2: internal default value is recommended. vln1: internal default value is recommended. voff: internal default value is recommended. v ref 1: internal default value is recommended. vlp: internal default value is recommended. vln_out: internal defaul t value is recommended. vln_amp: internal defaul t value is recommended. v ref : internal default value is recommended. adc calibration the MT9V403 contains a special self-calibrating cir- cuitry that enables it to reduce its own column-wise fixed-pattern noise. this calibration process consists of connecting a calibration signal to each of the 167 adc inputs and estimating and storing these 167 off- sets (as 7 bits) to subtract from subsequent samples. self-calibration automaticall y occurs after global logic reset (lrst_n) or the two-wire serial interface (register 12), and programs new offset values for each adc into calibration memory. these values may be different from those calculated in the previous calibration if there has been a change in environment (e.g., temper- ature). the accuracy of ca libration is approximately 1mv rms .
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 22 ?2004 micron technology. inc. table 6: pixel gain matrix adc calibration takes 146 sysclk cycles. nomi- nally, calibration should be initiated through the appli- cation of lrst_n, in which case the calibration takes place upon release of the lrst_n. some applications may require initiating calibration by asynchronously writing a one- to two-wire serial interface to register 12, in which case the calibration is delayed until the beginning of the next frame. calibration will continue to occur every frame until a zero is written to register 12. a timing diagram for the two-wire serial interface initiated calibration is shown in figure 28. in master mode and snapshot mode, during two- wire serial interface initiated calibration, row_valid goes high for 146 sysclk immediately after frame_valid goes high to indicate that the calibra- tion process is occurring. the output of the sensor is interrupted during the calibration process to prevent output noise from corrupting the calibration. after the calibration process is complete, row_valid goes registers 43-46 register 53 total gain 0000 0001 01.0 0000 0010 02.0 0000 0011 03.0 0000 0100 04.0 0000 0101 05.0 0000 0110 06.0 0000 0111 07. 0000 1000 08.0 0000 1001 09.0 0000 1010 0 10.0 0000 1011 0 11.0 0000 1100 0 12.0 0000 1101 0 13.0 0000 1110 0 14.0 0000 1111 0 15.0 0001 0000 0 16.0 0001 0001 0 17.0 0001 0010 0 18.0 0000 0001 10.5 0000 0010 11.0 0000 0011 11.5 0000 0100 12.0 0000 0101 12.5 0000 0110 13.0 0000 0111 13.5 0000 1000 14.0 0000 1001 14.5 0000 1010 15.0 0000 1011 15.5 0000 1100 16.0 0000 1101 16.5 0000 1110 17.0 0000 1111 17.5 0001 0000 18.0 0001 0001 18.5 0001 0010 19.0
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 23 ?2004 micron technology. inc. low and the normal data readout process com- mences when it returns high. for two-wire serial interface initiated calibration in slave mode, the first row_strt pulse of the calibration frame initiates the 146 sysclk calibration process. it is suggested that the user hold ld_shft_n high during this calibration process to minimize calibration noise. when the cali- bration is complete, ld_shft_n may be lowered to commence the normal frame readout process. figure 28: two-wire serial interface initiat ed calibration the calibration coefficients can be read from the MT9V403 and written to it, making it possible to fur- ther reduce column-wise fixed pattern noise by exter- nally calculating and writing the proper offset values to the MT9V403. for example, the user may choose to calculate the more precise offset values by averaging several frames and uploading the coefficients to the MT9V403. the user may also calculate coefficients for several temperature values and upload the appropri- ate values based on the environment. a special write-only two-wire serial interface regis- ter (register 15) is dedicated to the calibration data input. calibration data can be continuously written to this register with an eight-bit write. to write to the cali- bration register, the typical two-wire serial interface write sequence is adhered to, including address (regis- ter 15), followed by 167 eight-bit transfers (note that each coefficient utilizes the 7 lsbs of the eight-bit two- wire serial interface word). this writing process must be continuous (adc 1 to adc 167) and coefficients cannot be selectively written. in a similar manner, a special read-only two-wire serial interface register (register 143) is dedicated to calibration data output. calibration data can be con- tinuously read from this register with an 8-bit read. to read from the calibration register, the typical two-wire serial interface write sequence is adhered to, including address (register 143), followed by 167 8-bit transfers (note that each coefficient utilizes the 7 lsbs of the eight-bits two-wire serial interface word). this reading process must be continuous (adc 1 to adc 167) and coefficients cannot be selectively read. anti-eclipse circuit the MT9V403 includes a pixel memory reset pulse duration control. this control enables a mode where the reset of the pixel is held for a longer period of time. this can be implemented by setting bit 0 to 7 in regis- ter 13. in some extremely br ight lighting conditions, this extended reset may prevent the eclipse-like phe- nomena (black spots on a bright background) to which some cmos sensors are prone. 146 sysclk global logic reset frame_valid row_valid data [9:0] xxx first valid row
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 24 ?2004 micron technology. inc. figure 29: board connections note: 1. vln1, vlp, voff, vref, vref1, vln2, an d vref2 are generated on-chip, but user may disable internal bias (via two- wire serial interface) and apply external voltages to sensor . vref1drv is generated on ch ip but its internal bias can- not be disabled. vrst_pix and vrstlo w are not generated internally and ex ternal voltages must be applied. 2. all bias pins should be decoupled with 0.1f ceramic an d 10f electrolytic capa citors. (please see board connections.) capacitors should be placed as physically close as possible to the MT9V403 package. 3. digital outputs can drive standard cmos circuits with 30pf load, but less load capacitanc e results in less substrate noise on-chip. this is recommend ed to minimize load capacita nce for better noise performance. 12 22 v aa v aa 6 27 36 43 v dd v dd v dd v dd data0 3 data1 2 data2 1 data3 48 data4 47 data5 46 data6 42 data7 45 data8 40 data9 41 pixel data output 8 vref1drv 17 vln1 19 vlp 9 vref1 7 vref2 14 vtest1 analog +3.3v digital +3.3v 1.5k ? 1k ? 0.1f 10f 0.1f 10f analog +3.3v 0.1f 10f analog +3.3v 1k ? 1k ? 0.1f 10f analog +3.3v 1k ? 0.1f 10f analog +3.3v 1k ? 0.1f 10f analog +3.3v 1k ? 0.1f 10f analog +3.3v 1k ? 0.1f 10f analog +3.3v 1k ? 0.1f 10f analog +3.3v 1k ? 0.1f 10f analog +3.3v 1k ? 0.1f 10f 4 dgnd 5 dgnd 28 dgnd 34 dgnd 35 dgnd 44 dgnd 10 agnd 11 agnd 15 agnd analog ground digital ground controller interface 39 sdata 32 frame_sync_n 37 sysclk 29 expose 31 row_valid/ld_shft_n 38 sclk 30 frame_valid/row_strt 33 lrst_n 26 pg_n 25 tx 24 resmem vrstlow 23 vlns 18 vln2 21 vrst_pix 20 vref 16 voff 13 analog +3.3v digital +3.3v digital ground analog ground
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 25 ?2004 micron technology. inc. figure 30: propagation del ays for data output, frame va lid, and row valid signals sysclk dout(9:0) tplh d, tphl d tr sysclk frame_valid tplh f tr sysclk row_valid tplh l tr sysclk frame_valid tphl f tr sysclk row_valid tphl l tr
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 26 ?2004 micron technology. inc. electrical specifications table 7: ac electrical characteristics v pwr = 3.3 0.3v; t a = 25 c table 8: dc electrical characteristics v pwr = 3.3 0.3v; t a = 25 c note: 1. where indicated, internally generated biases are typically utilized. the pare nthetical number indicates typical value if external voltage is applied. 2. this device contains circuitry to prot ect the inputs against damage from high static voltages or electric fields, but the user is advised to take precaution s to avoid the application of any vo ltage higher than the maximum rated. symbol definition condition min typ max unit t plh d data output propagation dela y for low-to-high transition c load = 10pf 2 ns t phl d data output propagation dela y for high-to-low transition c load = 10pf 2 ns t plh l row_valid propagation delay for low-to-high transition c load = 10pf 2 ns t phl l row_valid propagation delay for high-to-low transition c load = 10pf 2 ns t plhl f frame_valid propagation dela y for low-to-high transition c load = 10pf 2 ns t phl f frame_valid propagation delay for high-to-low transition c load = 10pf 2 ns symbol definition condition min typ 1 max unit vln_amp internal/external 0.5 internal (0.7) 1.5 v vln2 internal/external 0.5 internal (1.1) 1.5 v vln_out internal/external 0.5 internal (0.8) 1.5 v vln1 internal/external 0.5 internal (0.7) 1.5 v vlp internal/external 1.5 internal (1.9) 2.5 v v ref internal/external 1 internal (1.6) 2 v v ref 2 internal/external 0 internal (1) 2 v v ref 1 internal/external 0 internal (1) 2 v voff internal/external 0 internal (0) 3 v vrst_pix external only 1 2.5 3.3 v vrstlow external only 0 0 - 0.4 1 v vtest external only - 0 - v ref 1drv internal only - open - v v ih input high voltage 2.5 v pwr + 0.3 v v il input low voltage -0.3 0.8 v i in input leakage current no pull-up resistor; v in - v pwr or v gnd -300 +300 ua v oh output high voltage v pwr - 0.2 v v ih output low voltage 100 220 mv i oh output high current 0.2 ma i pwr supply current clk_in = 42 mhz; default setting 20 ma
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 27 ?2004 micron technology. inc. two-wire serial bus timing the two-wire serial bus operation requires a certain minimum number of master clock cycles between transitions. these are specified below in master clock cycles. figure 31: serial host interface start condition timing figure 32: serial ho st interface stop condition timing note: all timing are in units of master clock cycle. figure 33: serial host interface data timing for write note: sdata is driven by an off-chip transmitter. figure 34: serial host interface data timing for read note: sdata is pulled low by the sensor, or allowed to be pulled high by a pull -up resistor off-chip. sclk 5 sdata 4 sclk 5 sdata 4 sclk 4 sdata 4 sclk 5 sdata
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 28 ?2004 micron technology. inc. figure 35: acknowledge signal timi ng after an 8-bit write from sensor figure 36: acknowledge signal timing after an 8-bit read to sensor note: after a read, the master receiver must pull down sdata to acknowledge receipt of data bits. when read sequence is complete, the master must generate a no acknowledge by leavin g sdata to float high. on the following cycle, a start or stop bit may be used. sclk sensor pulls down sdata pin 6 sdata 3 sclk sensor tri-states sdata pin (turns off pull down) 7 sdata 6
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 29 ?2004 micron technology. inc. electrical specifications table 9: image sensor characteristics t a = 25 c table 10: pixel array symbol parameter typ unit r i responsivity (adc v ref 1 = 1v) 1,800 lsb/lux-sec. dsnu dark signal non-uniformity 0.5 %rms v drk output referred dark signal 100 mv/sec dyn_i internal dynamic range 60 db prnu photo response non-uniformity 1 %rms n sat pixel saturation level 110,000 electrons ne input referred noise: overlapped conversion an d digital readout (200 fps) 98 electrons k drk dark current temperature coefficient 100 %/8c symbol parameter ty p unit resolution number of pi xels in active image 659 x 494 pixels pixel size x-y dimensions 9.9 m pixel pitch center-to-c enter pixel spacing 9.9 m pixel fill factor area of drawn active area 50 % shutter efficiency equals: 1-(l eakage into in pixel memory) 98.5 %
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 30 ?2004 micron technology. inc. figure 37: quantum ef ficiency ? monochrome figure 38: quantum efficiency ? color 0 5 10 15 20 25 30 35 350 450 550 650 750 850 950 1050 wavelength (nm) quantum efficiency (%) 0 5 10 15 20 25 350 450 550 650 750 850 950 1050 wavelength (nm) quantum efficiency (%) blue green (b) green (r) red
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 31 ?2004 micron technology. inc. figure 39: pixel array offset drawing note: 1. all dimensions are in millimeters. 2. tolerance on die placement is 0.25mm. 3. rotation <2. 4. tilt 2 mils. figure 40: package drawing ? top view note: 1. dimensions in mm. 2. 0.267 0.25 pin 1 14.22.013 (square) 8.915 9.149 6.61 4.97 1.3180.2 (1, 1) (502, 667) 13.16 sq 13.26 sq 14.07 14.52 42 31 43 30 6 7 18 19 max min ------------- -
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice.. MT9V403_ds.fm - rev. b 1/04 en 32 ?2004 micron technology, inc ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www .micron.com, customer comment line: 800-932-4992 micron, the m logo, the micron logo, and truesnap are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. figure 41: package view ? bottom view figure 42: package drawing - side view note: 1. dimensions in millimeters. 2. borosilicate: glass with refra ctive index: 1.52nm at 546nm. 3. data sheet designation no marking: this data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 1.75 2.25 1.02 typ 11.18 typ 0.51 typ 1.02 typ pin no.1 index 1.52 typ 30 6 43 48 42 18 19 31 7 glass 0.746 1.178 0.246 0.578 0.710 0.740 0.50 0.60 1.01 1.27 0.38 0.56 1.91 2.46 1.11 1.34 die max min ------------- -
1/2-inch vga (wit h freeze-frame) cmos active-pixel digital image sensor 09005aef80c07280 micron technology, inc., reserves the right to change products or specifications without notice. MT9V403_ds.fm - rev. b 1/04 en 33 ?2004 micron technology. inc. revision history rev b, ........................................................................................................................ .......................................................1/04 removed preliminary status updated figure 13 updated i in input leakage current specifications in the dc characteristics table added high-static note to dc characteristics table rev 0.7, preliminary .......................................................................................................... ..............................................8/03 initial release of document

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